Gate-all-around field-effect transistors (GAA-FETs) represent the leading-edge channel architecture for constructing state-of-the-art high-performance FETs. Despite the advantages offered by the GAA configuration, its application to catalytic silicon nanowire (SiNW) channels, known for facile low-temperature fabrication and high yield, has faced challenges primarily due to issues with precise positioning and alignment. In exploring this promising avenue, we employed an in-plane solid-liquid-solid (IPSLS) growth technique to batch-fabricate orderly arrays of ultrathin SiNWs, with diameters of D