THIẾT KẾ SAR ADC 10-BIT ENOB 57,9dB SNDR CÓ ĐỘ NHIỄU THẤP SỬ DỤNG BỘ SO SÁNH ĐIỀU CHẾ=A DESIGN OF LOW NOISE 10-BIT ENOB 57.9dB SNDR SAR ADC USING MODULATION COMPARATOR

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Tác giả: Dao Manh Binh, Hoang Nguyen, Van Lam Nguyen, Xuan Thanh Pham, Quang Viet Tran

Ngôn ngữ: vie

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Thông tin xuất bản: Tạp chí Khoa học & Công nghệ - Trường Đại học Công nghiệp Hà Nội, 2024

Mô tả vật lý: tr.192

Bộ sưu tập: Metadata

ID: 484206

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Bài báo này trình bày thiết kế của bộ chuyển đổi tương tự sang số (Analog-to-digital converter - ADC) thanh ghi xấp xỉ liên tiếp (Successive approximation-register - SAR) 10-bit số bit hiệu dụng (Effective Number of Bits - ENoB) 57,9dB tỷ lệ tín hiệu trên nhiễu và méo (Signal-to-noise and distortion ratio - SNDR) có độ nhiễu thấp sử dụng bộ so sánh điều chế, phù hợp cho các ứng dụng y sinh hiện đại. Trong thiết kế này, cấu trúc mạch khuếch đại hai tầng điều chế (Two-stage Op-amp Modulation - TOM) đã được sử dụng, bao gồm mạch khuếch đại hai tầng kết hợp với hai chopper đảo ngược cực đồng bộ. Mặc dù nhiễu 1/f và sự mismatch đã được giảm đáng kể bằng cách sử dụng mạch khuếch đại hai tầng với kỹ thuật điều chế, nhưng vẫn còn một số hạn chế. Cụ thể, kỹ thuật điều chế không hoàn hảo, kết hợp với sự mismatch phát sinh trong quá trình sản xuất, sẽ gây ra gợn sóng đầu ra dẫn đến chất lượng tín hiệu đầu ra thấp. Để khắc phục điều này, một kỹ thuật bù trừ sử dụng bộ tích phân ghép chéo khuếch đại hai tầng (Double Cross Integrator Amplifier - DCIA) được áp dụng trong ADC được đề xuất để tối ưu hóa hiệu suất của bộ so sánh, giảm thiểu sai số đầu ra và nhiễu. Sử dụng công nghệ CMOS 180nm, ADC SAR được đề xuất có diện tích hoạt động 0,55mm2. Với công suất 2,135mW và tham số đánh giá hiệu năng (Figure-of-Merits - FoMS) là 0,37 pJ/step.conv. Ngoài ra, ADC SAR được đề xuất đạt tỷ lệ tín hiệu trên nhiễu (Signal-to-noise ratio - SNR) là 56,40dB, SNDR là 57,9dB và tín hiệu tạp âm và méo (Signal-to-noise ratio and distortion - SINAD) là 56,40dB. Hơn thế nữa, bài báo còn đạt được ENoB là 9,08-bit.This article presents a design of low noise 10-bit Effective Number of Bits (ENoB) 57.9dB Signal-to-noise and distortion ratio (SNDR) Successive approximation-register (SAR) Analog-to-digital converter (ADC) using modulation comparator, suitable for modern biomedical applications. In this design, a Two-stage Op-amp Modulation (TOM) has been applied, which consists of a two-stage op-amp combined with two synchronized polarity-reversing choppers. Although 1/f noise and mismatch effect have been significantly reduced by using two-stage op-amp with modulation technique, there are still some limitations. In particular, modulation technique is imperfect, combined with offsets caused during the manufacturing process, will cause output ripple leading to low output signal quality. To overcome this, a compensation technique using two-stage Double Cross Integrator Amplifier (DCIA) are applied in the proposed ADC to optimize comparator performance, minimize offset and noise. Using 180nm CMOS technology, the proposed SAR ADC needs a 0.55mm2active area. With a power of 2.135mW and a Figure-of-Merits (FoMs) of 0.37 pJ/step.conv. In addition, the proposed SAR ADC achieves a Signal-to-noise ratio (SNR) of 56.40dB, a SNDR of 57.9dB, and a Signal-to-noise ratio and distortion (SINAD) of 56.40dB. Furthermore, this work attains an ENoB of 9.08-bit.

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