Today, there are often two-level cache (L1, L2 cache) in multi-core processor architectures now with individual L1 cache and individual or shared L2 cache for the cores. When the number of cores in the processor increases, the resource disputes in the L2 cache are very large, increasing latency and memory access time. In this paper the authors use Generalized Stochastic Petri Nets (GSPN) to analysis, evaluate and compare the performance of multi-core processor chips that have 2-levels cache organization (L1, L2 cache with L2 cache shares for cores) and 3-levels cache organization (L1, L2 and L3 cache in which L3 cache shares for cores), through which, choosing the best multi-level cache organization suits architecture of multi-core processors. Approved processing multithread per core, the simulation results indicate that performance of the multi-core processor chip with 3-levels cache is significantly enhanced multi-core process chip with 2-levels cache processor chip.