This is a design of a low power 6-bit 2 GS/s flash ADC based on 0.13um technology from TSMC. With the demand to run in high speed, the analog part is designed with fully pipelined. The reset switches controlled by clock are also inserted into a preamplifier stage, 2 stages of comparators for fast overdrive recovery. Sense amplifier is added to the comparator stage to improve the overdrive recovery and reduce the tail current for latched comparators to reduce the power. The simulation results show that with input signal is 994 MHz, the SNDR and ENOB reach 35.944 dB and 5.725 bits respectively at 2 GS/s and consumed about 112 mW with 1.2 V supply, achieving a FoM of 1.06pJ/conversion-step.