Integrated circuits (ICs) are more and more difficult to design due to their complexity and requirement of shorl time-to-market. A modem IC is designed as a System-on-a-Chip (SoC) based on intellectual properly (IP) cores. In recent design methodology, a SoC is built by integrating many reusable IPs from different parlies. This methodology helps to improve the design productivity and the time-to-market of a chip. However, it creates many difficulties for the verification process as the IP cores must comply with the communication standards used in the SoCs. Verifying that a module complies with the standard requires as much efforl as designing a new module. In this paper, the authors develop a Verification IP (VIP) core for DDR2 compliance verification. Interval properly checking (IPC) is used to formally verify that the operations of an open source DDR2 SDRAM Controller comply with the standard. The main contribution of the paper is the re-useable VIP that can be parameterized to verify different configurations of the DDR2 controller. In addition, for the first time, a DDR2 controller has been formally verified without any manual abstraction. As a consequence, the authors were able to detect an error in the DDR2 SDRAM controller.