The details of design and implementation of division, square root in single/double precision floating point on FPGA are presented. This study gives the design, implementation on FPGA with lower output latency, much smaller size in ALUT, DLR, and ALM than Altera's design. For the maximum frequency consideration, this study obtains better result only in division operation with single precision floating point. The choice of this study or Altera's design in a system should be considered due to the maximum frequency of system or the FPGA size.