In parallel processing systems, the efficient use of system resources is an important requirement. Improving performance and increasing speed are related to many issues, both hardware and software [1,2]. The analysis of processing system operation shows which affects the performance and speed of processing system: During referencing to memory, the processor uses only a command cycle in order to require to read or write data into memory, then wait for the completion of memory cycle before next memory access. Therefore, CPU speed is not taken full advantage
memory access conflicts occur when two or more components simultaneously access to a memory location. This paper proposes the method of controlling counter restructure to meet the requirements of information processing speed. The model used is a restructure controller with FPGA technology. The solution of speed increase is done by maintaining the maximized chain of memory access requests.