Emerging two-dimensional (2D) semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level thickness. As the stacking process advances, the complexity and cost of nanosheet field-effect transistors (NSFETs) and complementary FET (CFET) continue to rise. The 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems (IRDS) (2022, https://irds.ieee.org/ ), but not publicly confirmed, indicating that more possibilities still exist. The miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area, power consumption and speed. In this study, a comprehensive framework is built. A set of MoS