In this paper, we present the logic designs of two FPGA hardware programming algorithms implemented for a Coherent Doppler Lidar system used in wind sensing. The first algorithm divides the received time-domain signals into segments, each corresponding to a specific spatial resolution. It then calculates the power spectrum for each segment and accumulates these spectra over 10,000 pulse returns. The second algorithm computes the autocorrelation of the received signals and accumulates the results over the same number of pulses. Both signal pre-processing algorithms are initially developed as logic designs and compiled using the Xilinx System Generator toolset to produce a hardware VLSI image. This image is subsequently programmed into an FPGA. However, the hardware implementation of these algorithms presents several challenges: (1) bit growth: multiplication operations in the binary number system significantly increase the number of bits, complicating hardware implementation. (2) Memory constraints: onboard RAM arrays of sufficient size are lacking for accumulating vectors of the calculated Fast Fourier Transforms (FFTs) or autocorrelations. (3) Signal drive issues: large fan-out in the logic design leads to significant capacitance, restricting the driving capabilities of transistor output signals. This article discusses the solutions devised to overcome these challenges. Additionally, it presents atmospheric wind measurements obtained using the two algorithms.